Job responsibilities :
• Design from Gate-level netlist to GDSII (include DFT, floor plan, placement, CTS, routing, power analysis, SI analysis, STA, physical verify, XRC)
• Support IC design teams for timing closure
• (Semi-Custom) Focus on structured circuit design, layout, characterisation, flow automation and physical design of high-speed and low-power data path subsystems
• (Semi-Custom) Support IP development (physical design, collateral generation, flow development) and PPA quantification
• (Semi-Custom) Support block layout using custom/semi-custom/std cell libraries
• (Semi-Custom) Support block level floor planning using custom and/or tiling techniques
Job requirements :
• Bachelor or higher degree in Electronic/Computer Engineering with preferably solid knowledge in digital IC design
• Good understanding in digital IC design flow especially logic synthesis, timing analysis and physical design
• Good understanding of computer system architecture
• Familiar with Encounter or ICC
• Proficiency in scripting and flow automation Cross functions physical design, DC synthesis, clocking, std cell, power gating, IR/EM analysis, collateral generation
• Good command of written and spoken English
• Good team player with strong communication skills